Metallization method for silicon solar cells

ABSTRACT

A method of forming contacts on a surface emitter of a silicon solar cell is provided. In the method an n-type diffusion of a surface is performed to form a doped emitter surface layer that has a sheet resistance of 10-40 Ω/□. The emitter surface layer is then etched back to increase the sheet resistance of the emitter surface layer. Finally the surface is selectively plated. 
     A method of fabrication of a silicon solar cell includes performing a front surface emitter diffusion of n-type dopant and then performing a dielectric deposition on the front surface by PECVD. The dielectric deposition comprises:
         a. growth of a thin silicon oxide;   b. PECVD deposition of silicon nitride to achieve a silicon nitride.       

     The silicon is then annealed to drive hydrogen from the silicon nitride layer into the silicon to passivate the silicon.

CROSS REFERENCE TO RELATED APPLICATION

This application is the 35 U.S.C. §371 national stage of PCT applicationPCT/AU2010/001421, filed Oct. 25, 2010, which claims priority to and thebenefit of Australian Patent Application No. 2009905210, filed on Oct.26, 2009, both of which are hereby incorporated by reference in theirentireties.

COPYRIGHT NOTICE

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TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to the field of solar cellfabrication and, in particular, to an improved metallization method forsilicon solar cells.

BACKGROUND OF THE INVENTION

In order to extract current from solar cells it is necessary to formmetal contacts to both the n-type and p-type material of the device. Onemethod frequently used for forming these metal contacts is metalplating. This is a an attractive method for forming metal contacts tosolar cells because of its potential low cost and for forming narrowlines compared with that of screen-printed silver which is used for mostcommercially produced silicon solar cells. Electroless plating of nickeland then copper was successfully used by BP Solar in their manufactureof Saturn silicon solar cells.

Metal plating involves the reduction of metal ions from a solution toform a metal deposit on the solar cell. Typically, metal deposits areformed at cathodic sites on the cell (i.e., where there exists a sourceof electrons). This source of electrons can be provided by a reducingagent in the plating solution, in a process called electroless plating,or from electrons generated, at least in part, by the photovoltaiceffect when a solar cell is exposed to light in a process called“light-induced plating” (LIP) or photoplating.

Typically, prior to metallization openings (e.g., grooves) are formedthrough a dielectric layer (silicon dioxide or silicon nitride) toexpose regions of n-type silicon. The openings can be formed usinglaser-scribing or other patterning techniques, such as photolithography,and can involve either in-situ doping or subsequent furnace doping ofthe silicon exposed at the base of the grooves to result in aheavily-doped silicon region at the base of the grooves. This heavydoping at the base of the grooves enables ohmic contacts to be formedbetween deposited metal and the silicon. When metal plating, thepatterned dielectric layer, provided it is of high enough quality, actsas a mask for the deposition of metal with metal, in ideal situations,only plating to the silicon regions exposed by the patterning process(e.g., at the base of the grooves).

However in commercial production, for cost, simplicity, throughput andthe avoidance of high temperatures, such dielectric layers are often notof good enough quality to act as a plating mask, leading to unwantedlocalised areas of spurious plating in areas other than where requiredfor the metal contacts. For example, a common problem encountered in themetal plating of silicon solar cells employing a silicon nitridedielectric masking layer, and in particular where the silicon nitridehas been deposited by remote plasma enhanced chemical vapour deposition(PECVD), is the formation of spurious unwanted metal deposits over thedielectric layer, in addition to the metal deposited in the grooves. Thephenomenon is often referred to as “ghost plating”. In addition toincreasing the effective shading for the solar cell, “ghost plating” isalso undesirable because it can result in shunts, especially when themetallization process includes a metal sintering step to further reducethe contact resistance of the metal contacts.

To some extent the “ghost plating” problem can be solved by growing athin (10-15 nm) silicon dioxide layer on the diffused silicon beforedepositing the silicon nitride layer. Although, this method can beeffective in eliminating “ghost plating” it has several disadvantages.First it typically requires an additional high-temperature process whichis undesirable for many lower-quality silicon substrates becauseincreased exposure to high temperatures reduce carrier lifetimes.Furthermore, it increases the overall cost of fabrication process by theincreased wafer handling. Second, it limits the extent to which thehydrogen from the silicon nitride layer can be used to passivate defectsin the silicon substrate. The latter point is particularly relevant tomulticrystalline wafers which exhibit many defects due to the presenceof grain boundaries in the wafers. Multicrystalline wafers are popularcommercial substrates due to their low-cost and so this secondlimitation is particularly pertinent.

SUMMARY OF THE INVENTION

According to a first aspect, the present invention consists in a methodof forming contacts on a surface emitter of a silicon solar cell, themethod comprising:

n-type diffusion of a surface to form a doped emitter surface layer thathas a sheet resistance of 10-40 Ω/□;

etching back the emitter surface layer to increase the sheet resistanceof the emitter surface layer; and

selectively plating the surface.

The selective plating may be achieved by forming a plating mask andplating through the mask. Alternatively, the selective plating may beachieved by creating surface regions where plating is required which aremore highly doped than the remainder of the surface and plating thesurface whereby plating selectively forms on the more highly dopedregions.

The etching back step may results in an emitter surface layerresistivity in the range of 100-150 Ω/□.

The emitter doping step may be achieved using a POCl₃ diffusion schemein a diffusion furnace and the wafers may be placed back-to-back priorto loading them into the diffusion furnace to minimize doping of theback surfaces. The heavy front surface diffusion may be achieved in oneexample by:

(i) performing a of pre-oxidation diffusion for 5 mins at 890° C.; and

(ii) performing a further diffusion in the presence of POCl₃ for 30 minsat 890° C. to achieve a 10-20 Ω/□ sheet resistance on the front surface.

The diffusion source may also be a spin-on diffusion source.

The diffusion process may produce a sheet resistance of >100 Ω/□ on therear surface.

Preferably the diffusion is performed to achieve a uniform diffusionwith <10% variation in sheet resistance across the front surface ofwafers.

The etch-back process may be achieved by immersing the diffused wafersin an etchant solution. The etch-back can also be done by just sprayingthe etchants onto the wafer surface rather than immersion in liquid. Onesuitable arrangement is a Trilogy etch (126 parts nitric acid, 60 partswater and 5 parts 40% (w/v) ammonium fluoride) performed at 20° C. for40 seconds. The etch-back process may also be achieved by performing anetch in a solution comprising potassium permanganate, water and HF.Alternatively an etching solution which preferentially etches morehighly doped n-type silicon than lightly doped silicon may be used, suchas a molar composition of silicon etching solutions comprising HF,nitric acid and acetic acid. In particular the etching solution maycomprise 1 part HF, 50 parts nitric acid and 100 parts acetic acid.

The selective plating may be achieved by forming a plating mask andplating through the mask. Alternatively, the selective plating may beachieved by creating surface regions where plating is required which aremore highly doped than the remainder of the surface and plating thesurface whereby plating selectively forms on the more highly dopedregions.

According to a second aspect the present invention consists in a methodof fabrication of a silicon solar cell comprising:

-   -   i. performing a front surface emitter diffusion of n-type dopant        to achieve a finished emitter sheet resistivity of 50-250 ohms        per square;    -   ii. performing a dielectric deposition on the front surface by        PECVD comprising:        -   a. growth of a thin 5-30 nm oxide;        -   b. PECVD deposition of an Anti-Reflection Coating (ARC) and            hydrogen source;    -   iii. screen-print rear (non-light receiving) surface with        aluminium for the rear contact, followed by firing;    -   iv. annealing the silicon to drive hydrogen from the silicon        nitride layer into the silicon to passivate the silicon after        the rear contact firing step (iii) at least.    -   v. performing a localised laser melting of the wafer top surface        to simultaneously melt and dope the light receiving surface of        the silicon, creating the heavily doped n+ regions in locations        where front surface metal contacts are to be formed, while        destroying the overlying dielectric layers to expose the doped        silicon surface of the n+ regions;    -   vii. plating a layer of nickel over the laser doped n+ regions.

The solar cell is preferably manufactured from multicrystalline silicon.

The front surface emitter diffusion of n-type dopant is preferablyperformed to achieve a finished emitter sheet resistivity of 80-160 ohmsper square (nominally 100 ohms per square).

The thin silicon oxide layer is preferably grown to a thickness of 10-20nm and may be grown thermally in a belt or tube furnace. Alternativelythe thin silicon oxide layer may be grown by PECVD.

The ARC and hydrogen source may comprise one or more layers of siliconnitride (SiN_(x)), aluminium oxide (Al₂O_(x)), titanium oxide (TiO₂) oranother material with similar suitable properties. In particular thematerial should have a similar refractive index to SiN_(x) (approx 2.0in air), and can simultaneously contain significant amounts of hydrogenthrough the deposition process to be able to provide the atomic hydrogensource during subsequent anneals (though this might be achieved using aplurality of layers with different characteristics to achieve thecombined requirement). In this way, the thin oxide would provide thesurface passivation (in conjunction with the H+ through the anneal) andprotect against ghost plating and reduce laser damage during the laserdoping, while the overlying layer would provide the optical requirementsfor antireflection and the hydrogen source for the anneal. The opticalthickness of the ARC needs to be effectively be one quarter wavelengthof the dominant light colour in sunlight which is about 600 nm (in air).It is therefore the product of the refractive index and the layerthickness that needs to be the same for the different materials. Howeverto be a good single layer ARC, the refractive index needs to be about2.0 (to be sandwiched between silicon and air) in which case thethickness needs to be about 75 nm. This applies to all the mentionedmaterials (SiNx, Al2Ox and TiO2 which can all be deposited withrefractive index of about 2).

The ARC layer or layers preferably have a thickness of 65-75 nm and maybe a single hydrogen rich layer. Alternatively the ARC layer maycomprise at least two layers as follows:

-   -   i. 80-120 angstroms of hydrogen rich material;    -   ii. 550-650 angstroms of a material of refractive index 2.0-2.1;

The ARC will preferably comprise silicon nitride.

The anneal may be performed at a temperature in the range of 350 to 720°C. for 0.5 to 20 mins. Preferably the anneal may be performed at atemperature in the range of 350 to 500° C. for 5 to 20 mins or in therange of 500 to 720° C. for 0.5 to 8 mins and in particular it may beperformed at a temperature in the range of 380 to 420° C. for 8 to 12mins.

The laser doping of the silicon, in locations where front surface metalcontacts are to be formed, may performed to achieve a junction depth inthe range 0.1 to 12 microns and preferably in the range 1 to 5 microns.The laser doping of the silicon, in locations where front surface metalcontacts are to be formed, may result in a localised sheet resistivityin the formed n+ regions following melting and/or evaporation of thesilicon in the range 0.2 to 200 ohms per square and preferably in therange 1 to 40 ohms per square.

The nickel plated to the n+ regions may be sintered at 150-500° C. for0.2 to 20 mins and preferably at 350-400° C. for 1-3 mins. The nickelplated to the n+ regions may also be sintered at 350 to 720° C. for 0.5to 20 mins and preferably at 350 to 500° C. for 5 to 20 mins or 500 to720° C. for 0.5 to 8 mins and incorporates the annealing step topassivate the silicon. In particular nickel may be sintered at 380-420°C. for 8 to 12 mins while incorporating the annealing step to passivatethe silicon. This duration is longer than normally considered optimalfor Nickel sintering in laser doped solar cells and will therefore leadto the nickel penetrating further into the n+ laser doped silicon andpotentially to the junction region where deterioration in the electricalperformance of the device can result. To avoid this, the laser doping ispreferably done in a way where the junction between the n+ laser-dopedsilicon and the p-type wafer is deeper, such as can be achieved with alaser that keeps the silicon molten for longer such as a cw laser. Inparticular, the junction needs to be at least 2 microns deep andpreferably in the range of 4 to 10 microns to accommodate these combinedannealing/sintering conditions.

The firing of the rear screen printed contact may be performed in a beltfurnace and may be performed at temperatures in the range of 650-1,000°C. The firing of the rear screen printed contact will preferably beperformed at 800-880° C.

The solar cell is preferably formed on a p-type wafer and an Isotropictexturing step may be performed on the front (or light receiving)surface of the p-type wafer prior to performing the front surfaceemitter diffusion

Preferably a step to perform a rear surface etch/edge junctionisolation/psg removal from front surface occurs after the emitterdiffusion step.

Prior to the laser doping step, a dopant containing source may be formedon the top surface over the oxide and silicon nitride layers.Alternatively the dopant source may be supplied to the top surface overthe oxide and silicon nitride layers during the laser doping step. Thedopant source preferably comprises a phosphorus source. The dopantsource may be supplied to the top surface in a gaseous state or a liquidstate during the laser doping step.

In one embodiment, the dopant source may be supplied to the top surfaceover the oxide and silicon nitride layers as a liquid jet through whicha laser beam is directed onto the top surface during the laser dopingstep. The liquid jet may be generated by the nozzle unit into which thelaser beam is coupled such that it may be guided by total internalreflection within the liquid jet towards the target. The liquid jet maycomprise phosphoric acid.

A dilute HF dip is preferably performed to remove any oxide or othersurface layer on the heavily phosphorus doped silicon after the laserdoping step.

The Nickel plating over the laser doped n+ regions, for the frontsurface contacts; may be performed to provide an nickel thickness in therange of 0.01 microns to 10 microns but preferably in the range 0.1 to 1microns.

Plated layers of Copper and Tin (or Silver) may be formed over theNickel.

The layers of copper and tin (or silver) may be plated over the nickelplating to a thickness in the range of 1 microns to 25 microns butpreferably in the range 5 to 15 microns (nominally 8 microns). A thinsilver layer may then be plated over the other metal layers to cap andprotect the copper and tin layers. The silver plating may have athickness in the range of 0.005 microns to 1 microns but preferably inthe range 0.01 to 0.1 microns (note, the copper and or tin can beeliminated and replaced by a Silver layer of the same dimensions as thecopper and or tin layer it replaces).

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example,with reference to the accompanying drawings in which:

FIG. 1 is a flow chart showing the process that results in spuriousunwanted metal being deposited on the silicon nitride surface duringmetal plating of cells;

FIG. 2 is a flow chart showing the process of the preferred arrangementof the invention that eliminates the deposition of spurious unwantedplating on the silicon nitride surface during metal plating of cells;

FIG. 3 compares the doping profiles of the shallow, lightly-diffusedemitter (that results from the process depicted in FIG. 1) with thatobtained from the deeper, more heavily-diffused emitter (that resultsfrom the process depicted in FIG. 2);

FIG. 4 is a flow chart showing an alternative embodiment of theinvention used to form a selective-emitter cell structure.

FIG. 5 illustrates a Solar cell with a selective emitter structure andmetal contact formed in self-aligned method following the laser dopingof the heavily doped regions beneath the metal contact. The manufactureof this solar cell may also incorporate one of the improved laseroperation methods described herein;

FIG. 6 schematically illustrates the arrangement of a laser and liquidjet when used to process a surface of a target; and

FIG. 7 schematically illustrates a laser operated to heat a target in agaseous environment to process a surface of a target.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 depicts a process for fabricating laser-doped p-type siliconsolar cells. This process has been developed with a view to fabricatingsilicon solar cells which demonstrate higher efficiencies than thecurrent industry-standard screen-printed cells but at a comparable costper unit area. These cells are characterized by a shallow, lightly-dopedn-type emitter which improves the cell's blue-light response from thatof a standard industrial screen-printed solar cell. The fabricationprocess 100 employs metal plating to form the front metal contacts andwould benefit from advances that eliminate “ghost plating” that occursduring the metal plating step. The steps of the fabrication process 100are first described and then compared with the fabrication process ofthe preferred arrangement 200 (see FIG. 2), in which the occurrence of,“ghost plating” has been eliminated.

The fabrication process 100 comprises a texturing step 105 whichinvolves the formation of a texture on the wafer surfaces to reducesurface reflection and enhance light trapping inside the cell.Typically, alkali texturing is used for mono-crystalline wafers and acidtexturing for multi-crystalline wafers. After texturing, in step 110 thewafers are cleaned and then immersed in a 5% hydrofluoric acid (HF)solution to remove any native oxide that may have formed on the siliconsurfaces. In step 115, an n-type emitter is formed on the front surfacesuch as by using a standard POCl₃ furnace diffusion or diffusion from aspin-on or spray-on diffusion source such as phosphoric acid. In orderto maximize the blue-light response of the cells, it is desirable todiffuse less phosphorus into the surface of the silicon during theemitter formation compared to screen-printed cells to achieve a sheetresistance of 100-150 Ω/□. Such commercial emitter diffusion processes,despite the much higher sheet resistivity compared to screen-printedcells, still have surface phosphorus doping concentrations similar tothose for screen-printed solar cells in the vicinity of the solidsolubility of phosphorus in the silicon at the diffusion temperaturesuch as shown in FIG. 3. The junction depths though are significantlyless.

After the diffusion, in step 120 the cells are then immersed in a 2.5%HF solution to remove the phosphosilicate glass (PSG) or dopant sourcethat remains on the surface after the diffusion. The rear surface isthen etched back in step 125 to remove any unwanted diffusion on therear surface and also to isolate the junction at the edges.

The silicon nitride dielectric layer is then deposited in step 130.Typically in industrial environments this deposition is done usingremote PECVD at a temperature of 400° C. to result in a final layer ofthickness about 75 nm and refractive index of about 2.0. In addition, toacting as an antireflection coating for the cells, the silicon nitridealso serves to passivate the underlying silicon thus enabling highercell voltages.

The rear surface electrode is formed by screen printing an aluminiumpaste on the rear surface of the cell in step 135. The cells are thentypically fired in a belt furnace at a temperature of 800° C. for lessthan a minute. This firing treatment is above the aluminium/siliconeutectic temperature and therefore results in aluminium diffusing intothe molten silicon to form a more heavily doped p+ layer which acts as aback-surface-field.

Front metal contacts can then be formed by using a laser tosimultaneously scribe and heavily-dope openings in the front dielectricsilicon nitride layer. This process, in step 140, is referred to aslaser-doping and is typically achieved by coating the silicon nitridesurface with a surface layer of phosphorous dopant (e.g., phosphoricacid) before using the laser to scribe the openings. In this process,the heat from the laser locally melts the silicon and enables thephosphorous atoms to diffuse into the silicon before it re-solidifies.Using this technique, regions typically doped to a sheet resistance of10-20 Ω/□ can be formed in the base of the grooves thus enabling ohmiccontacts with low contact resistance to be formed between the siliconand the metal.

Clearly simultaneous heavy doping and scribing can also be performedusing other techniques, such as liquid chemical processing (LCP) asdescribed in [D. Kray et al., Laser Chemical Processing (LCP)—Aversatile tool for microstructuring applications, Appl. Phys. A. 93,99-103 (2008)]. Also, an equivalent process that involves first etchingor scribing the openings in the silicon nitride layer and then achievingthe heavy doping at the base of the grooves by performing an additionalheavy diffusion step with the silicon nitride acting as a mask for theheavy diffusion that limits the phosphorous dopant atoms to just thearea exposed in the base of the grooves. The latter process was employedby BP Solar in their manufacture of Saturn cells, however in this casethey used low pressure CVD instead of the more commonly-used PECVDprocess.

The final step of this fabrication process 145 involves the plating ofmetal to the exposed regions at the base of the grooves. The plating canbe achieved using electroless, electroplating or light-induced metalplating. A number of different metal combinations can be used, binperhaps the most attractive combination from the perspective of reducedcost is the use of a thin layer of nickel to form a barrier layer with athicker layer of copper being deposited to form highly-conductivefingers which are capable of the carrying the current from the solarcell to an electrical connection. Preferably, the nickel layer issintered to form a nickel silicide layer which further reduces thecontact resistance of the metal silicon interface. This sinteringprocess can either be performed after the nickel deposition step andbefore the copper is deposited or after the copper deposition process.

A considerable problem that is experienced with the use of thefabrication process 100 is that of spurious unwanted plating of themetal to regions of the silicon nitride surface other than the grooves.This spurious plating is observed when using either electroless platingor LIP processes in the metal plating step 145. This phenomenon has beenreferred to as “ghost plating” and is undesirable because of theincreased shading (due to the unwanted metal deposits) but also possibleshunting that can occur when nickel can permeate the shallow p-njunction of the non-groove areas during the heating associated with theformation of a silicide.

A new process will now be described which can ameliorate the problem of“ghost plating”, whilst potentially simultaneously avoiding the need fora separate edge junction isolation process and whilst retaining all theother attractive aspects of the above-described fabrication process 100.It has been enabled by a fundamental understanding of the cause of the“ghost plating” to be due to a high surface concentration of(phosphorous) dopants in the diffused silicon (i.e., after step 110 inprocess 100). This high concentration of phosphorous dopants appears tobe unaffected by the PSG removal step 115 and therefore, in the absenceof a high quality dielectric masking layer attracts unwanted or spuriousmetal deposition during metal plating processes. This problem has beenaddressed in the preferred arrangement of this invention which isdepicted by fabrication process 200 in FIG. 2.

The fabrication process 200 is essentially the same as process 100 withthe exception of steps 115 and 125 which are replaced by steps 205 and210, respectively. In step 205 the phosphorous diffusion process isaltered to result in amore deeply doped emitter top surface layer thathas a final sheet resistance of 10-40 Ω/□ rather than the 100-150 Ω/□emitter that is formed in step 115 of process 100. This is achievedusing a POCl₃ diffusion scheme by placing the wafers back-to-back priorto loading them into the diffusion furnace to restrict the amount ofphosphorus able to get to the rear surface of the wafers compared to thefronts. For spin-on diffusion sources, the rear surfaces naturallyreceive less phosphorus, leading to significantly higher sheetresistivities, with shallower junction depth compared to the frontsurface. The heavy front surface diffusion using a POCl₃ diffusionscheme preferably involves:

-   -   (i) 5 mins at 890° C. of pre-oxidation diffusion (to form a base        layer in which the P₂O₅ dopant can diffuse); and    -   (ii) 30 mins at 890° C. in the presence of POCl₃ to achieve the        preferred 10-20 Ω/□ sheet resistance on the front surface and        typically >100 Ω/□ on the rear surface. Preferably, a uniform        diffusion with <10% variation in sheet resistance across the        front surface of wafers is performed. This diffusion scheme        results in doping profile for phosphorus as shown in FIG. 3        where it is compared with the shallower profile that is obtained        using step 115 of process 100. In the case of step 205 the        junction is now located more than 1.5 μm from the surface, as        compared to the junction depth of ˜0.3 μm that results with the        shallower diffusion of step 115. In both cases, however the        phosphorus concentration at the surface is similar and between        10²⁶ and 10²⁷ m⁻³.

In the diffusion process, as the dopant concentration is raised above10⁻³, a “kink” starts to appear in the doping profile and the tail ofthe profile extends deeper into the substrate as the surfaceconcentration is raised higher. This corresponds to an apparent increasein the diffusion coefficient despite a constant diffusion time andtemperature. This phenomenon is also known as the “emitter (orphosphorus)-push effect”. This effect can be utilized to obtain a deepjunction on the front surface of the wafer, while a shallower junctioncan result on the rear surface by restricting the phosphorus access tothe rear surface by either only applying the dopants to the frontsurface or else locating wafers back-to-back with an adjacent wafer andthereby keeping the phosphorus concentration within the silicon at a lowenough value to avoid the enhanced diffusion coefficients that resultfrom the “emitter push effect”.

In step 210 an etch-back process is performed to remove a surface layerfrom the heavily-diffused silicon surface. As shown in FIG. 3, this etchback process can be optimized such that the final sheet resistance is100-150 Ω/□ (i.e., as desired for a lightly-doped emitter). However,unlike the dopant profile that results from the diffusion step 115 ofprocess 100, the new dopant profile of the etched-back surface has asignificantly lower surface concentration of phosphorous dopants (i.e.,<10²⁶ m⁻³). Furthermore, the etch-back process (step 210) also etchesthe rear surface to remove unwanted dopants from that surface andachieves edge isolation by removing almost all such dopants from therear due to the shallower junction compared to the front. Theseprocesses were performed as part of step 125 in fabrication process 100.

In the preferred arrangement the etch-back process is achieved byimmersing the diffused wafers in a Trilogy etch (126 parts nitric acid,60 parts water and 5 parts 40% (w/v) ammonium fluoride) at 20° C. for 40seconds. The etch rate for (100) silicon is quoted to be 150 nm/min (K.R. Williams. “Etch Rates for Micromachining Processing—Part II”, Journalof Microelectromechanical System, Vol. 12, No. 6, pp. 761778, 2003). Itis desirable to use etching solutions which etch crystalline siliconrelatively slowly to ensure that accurate timing of the etch-backprocess is possible. If necessary the etching rate can be furtherreduced by performing the etch-back at temperatures <20° C.

Alternatively the etch-back can be performed in other isotropic siliconetching solutions, such as solutions comprising potassium permanganate,water and HF, which etch silicon more slowly. However, although thisenables the etching time to be more carefully controlled, in many placesin the world disposal of permanganate can be problematic.

In further alternative arrangements, etching solutions whichpreferentially etch more highly doped n-type silicon than lightly dopedsilicon can be used. For example, it is known that the molarcompositions of silicon etching solutions comprising HF, nitric acid andacetic acid can be varied to adjust the etch rate and also selectivityto dopant level. U.S. Pat. No. 4,681,657, granted to Hwang et al.,describe the use of such a solution comprising 1 part HF, 50 partsnitric acid and 100 parts acetic acid that etches highly doped silicon25 times faster than lightly doped silicon. This composition shows asharp increase in etch rate when the dopant level is greater than 10²⁵min⁻³. Furthermore, this solution's etching rate for highly-dopedsilicon is only 44 nm/min making the etch-back process easier tocontrol.

Although the use of such selective etchants provides more controllableetch back and guaranteed removal of all the most heavily doped siliconfrom the regions where plating is to be avoided, this approach howeverfails to remove any unwanted phosphorus diffusion into the rear surfaceof the wafer, and therefore may still necessitate a separate edgejunction isolation process. Alternatively, the etch-back process caninclude a first etching step which only etches lightly (or un-doped)silicon, leaving the heavily-doped front surface untouched. When therear-surface doping has been removed then the abovementionedpreferential etch for heavily-doped regions can be used to morecontrollably etch back the front surface. Alkaline anisotropic etchescan be used in the etching step as heavily-doped regions tend topassivate quickly in these solutions and therefore are protected fromthe action of these etchants.

After the etch-back step 210 the remaining steps of the fabricationprocess 100 are performed with the only required difference in theprocedure being a slight increase in the PECVD time required to achievea silicon nitride layer of the same thickness as achieved in process100. The lower surface concentration of dopants, provided it is at leasta factor of two below the laser doped (or other) region to be metalized,appears to alleviate the need for a high quality masking layer for theLIP process, making it feasible to use standard PECVD of silicon nitrideor other suitable low cost antireflection coating layer such as titaniumdioxide, for both antireflection coating and plating mask. To ensure thephosphorus surface concentration differential of at least a factor oftwo (and preferably at least a factor of 10) is achieved between theregions to be plated compared to those needing to avoid plating, deeperjunctions than the typical 1 micron deep junctions typically formed inthe laser doped regions are desirable. A continuous wave laser has beenfound particularly effective at achieving such deeper junctions whilesimultaneously retaining the very high phosphorus concentrations, withdepths in the range of 1 to 20 microns demonstrated. Such deeper laserdoped junctions therefore make it easier to get greater variation in thesurface doping concentration by etching away more silicon, thereforeproviding greater protection against spurious plating to the lighterdoped surface regions. In addition, the greater the variation in thesurface doping concentration, the lower the quality of the masking layerthat can be tolerated such that in the extreme, sufficient variation canfacilitate localized plating to the heavily doped laser doped regionswithout even requiring any masking layer for the lightly doped regions.At the other extreme, with a high enough quality masking layer such asprovided by high temperature thermal oxidation of the silicon or hightemperature CVD such as of silicon nitride, virtually no concentrationvariation is required between the exposed regions to be plated and thosethat are masked and therefore not to be plated. A further factor thatcan be used to reduce the required surface concentration variation for agiven masking layer quality is increasing the surface roughness of theregion to be plated. This can be done as part of the laser dopingprocess or as a subsequent chemical or mechanical process applied to theexposed silicon surfaces to be plated. For example, following the laserdoping process for the regions to be plated, provided the depth of thejunction is deep enough, a texturing solution can be used to roughen thesurface to enhance both its ability to be plated relative to smoothersurfaces as well as improving the adhesion of the subsequent metal tothe silicon surface in such regions.

As will be appreciated by someone skilled in the art, for a givenantireflection coating (surface dielectric) masking quality, there are arange of approaches that can be used to achieve the required variationin surface doping concentration necessary to prevent the masked areasfrom being plated while ensuring the unmasked areas are plated asrequired. Another example of such an approach is to diffuse the emitterdopants through an already patterned mask such that the masking layerrestricts the phosphorus penetrating into the silicon in such regions,reducing both the amount of phosphorus and the surface phosphorusconcentration relative to the unmasked regions that are to be metalized.

In another implementation of this general approach, the heavy doping ofregions to be metalized (such laser doping or alternative method) can becarried out prior to application of the antireflection coating. In thiscase if the antireflection coating layer is of too high a quality interms of its masking abilities, then no LIP plating will take place.However, with a layer of poorer masking qualities as would be normallyexpected from low cost, high throughout commercial processes, theheavily doped regions intermittently plate during the LIP process whilethe variation in surface doping concentration leads to the avoidance ofspurious plating to the regions with lower surface concentration. Such astrategy can be of benefit when there is a preference to reduce themetal/silicon interface area. Additional plating time can then be usedto facilitate plating across the dielectric surface to allow thelocalized dots of plating to join up to produce continuous lines ofplated metal above the heavily doped regions if desired.

In another implementation of this general approach, the conductivity ofthe preferred regions for plating can be enhanced by a range oftechniques rather than by using techniques such as an etch-back of theregions not to be plated so as to reduce their conductivity. Forexample, regions to be plated could be coated by conductive inks orpastes that could comprise a range of conductive materials or particlessuch as highly doped silicon particles or even metal particles. Suchprinted or deposited layers often require a heat treatment to achievebest electrical properties, following which their conductivity exceedsthat of the rest of the doped surface of the semiconductor, thereforefacilitating plating selectively to the more conductive regions eitherwith or without a masking layer.

In the preferred arrangement described in FIGS. 2, the metal platingstep 145 is performed by LIP of nickel, followed by a nickel sinter stepat 350° C. for 5 minutes, and then a final LIP of copper. In theseplating operations, the wafers are immersed in plating, solutionscomprising a source of nickel and copper ions, respectively. The rearaluminium surface of the cell is electrically connected to a separateanode comprising the metal being plated. Care is taken to ensure thatthe depth of the solution between the light source and the wafer wasrestricted to ≦1 cm in order to reduce the amount of light absorbed bythe solutions before reaching the solar cell surface. The plated coppersurface of the metal contact is then preferably protected fromenvironmental oxidation by a final treatment in immersion silver.Alternatively, electroless plating or electroplating, or combinations ofelectro- and LIP processes can be used to form the metal contactswithout any observable “ghost plating” on the silicon nitride layer.

The key to this method is reducing the surface concentration of dopantsin the diffused silicon before depositing the silicon nitride or othercommercially viable antireflection layer. An alternative way ofachieving this reduced surface concentration of dopants involvesincreasing the duration of the pre-oxidation step. The thicker silicondioxide layer that results, slows down the rate at which phosphorusdopants enter the silicon substrate while giving time for dopants thathave already diffused into the silicon to diffuse further.

The present method can also be used advantageously to fabricateselective-emitter solar cells that do not require a second doping step.Instead of using a laser to simultaneously scribe openings in thesilicon nitride layer and heavily-dope the silicon that is exposed atthe base of these openings, a fluid deposition device can be used tofirst print a resist pattern on the heavily-doped front surface thatresults from step 205 in fabrication process 200, thus protecting theseregions from the etch-back process in step 210. Then rather than use alaser to form the openings through the silicon nitride layer in step 140in fabrication process 200, a fluid deposition device is used to etchopenings in the silicon nitride layer that align with the highly-dopedregions of silicon. This fabrication process 400 is shown in FIG. 4. Theonly variations from process 200 are (i) the insertion of step 405 whichinvolves the deposition of a resist pattern on the silicon surfacebefore the etch back process in step 205; and (ii) the replacement ofthe laser-doping step 140 with a patterned etching step 410. Steps 405and 410 will now be described in more detail.

In order to retain highly-doped regions from the initial diffusionprocess in step 205 only at the regions where front-contact openingswill be formed a resist material is deposited on the highly-dopedsurface in a pattern corresponding to the pattern of openings. Theresist material is preferably a silicon dioxide solar resist material,such as the inkjet printable isishape “SolarResist™”, as provided byMerck Chemical, but other spin-on-glass materials can also be used. Anadvantage of the preferably-used “SolarResist” material is that it canbe tempered in air and therefore does not require a heat treatment inorder to provide resistance to chemical etchants. Preferably thethickness of the deposited “SolarResist” material is 50-150 nm and morepreferably ˜100 nm.

Alternatively, polymer acid resist materials can also be used (e.g.,novolac resins, polymethylmethacrylic acid, etc.), however these resistmaterials typically require both a heating step to cure the polymer anda stripping process. Furthermore, they risk the introduction of organicresidues onto the surface before the silicon nitride deposition step.

Preferably, the “SolarResist” material is removed after the etch-backstep 210 by immersion of the wafers in a solution comprising 50% 7:1buffered oxide etch and 50% deionised water for 2-4 minutes, with theactual time depending of the final thickness of the deposited resistmaterial. Alternatively, the resist material can be retained andalthough it will affect the properties of the silicon nitride depositedover those regions, it can also assist in visually differentiating theheavily-doped regions from the lightly-doped regions at the patternedetching step 410.

The deposition of the resist material is preferably achieved using anaerosol jet printer, such as provided by Optomec, Inc. This depositionprocess results in deposits which can be very low in solvent contentbecause of the dehydration of the aerosol particles, and therefore notrequire additional heating processes to eliminate solvent. However,clearly other deposition devices such as inkjet printers can also beused. Preferably the resist pattern uses dimensions (e.g., line widths)that are slightly larger than the anticipated openings for the metalcontacts because the etch-back process in step 210 will result in someundercut etching below the edges of the resist.

Then in step 410, a pattern of openings for the metallization are thenetched in the silicon nitride. This etching process can be easilyaligned with the heavily-doped areas because the silicon nitride whichis deposited over the heavily-doped areas is visually evident andalignment between heavily-doped regions and the etching pattern can bereadily achieved using a camera integrated in the fluid depositiondevice. The method used to etch the openings (e.g., grooves) into thedielectric layer is described in WO/2009/094711 “Method of PatternedEtching of Selected Material” hereby incorporated by reference. Thethus-patterned grooves can then be metalized as described for step 145in fabrication process 200.

An alternative method of minimizing, with a view to eliminating, thepresence of “ghost plating” is to exploit the properties of the metalplating process to minimize the likelihood of the spurious plating. Theformation of metal deposits by the reduction of metal ions in a platingsolution is driven by the potential at the silicon surface. Althoughthis potential is largely due to the electrochemical potential over thecell in LIP, the surface potential also depends on properties of theinterface. The rate of an electrochemical reaction, such as thereduction of metal ions at the cathodic regions of the front surface,depends on the overpotential of the reaction. There are many sources ofoverpotential, and all sources contribute to the cathode having to bemore negative than the potential theoretically required to drive thereduction reaction.

Contributing sources of overpotential (for metal deposition in thefront-contact grooves) include concentration and resistance factors.These sources of overpotential are reduced for more heavily-dopedsilicon surfaces. Simply put, the higher concentrations of electrons inthe more-heavily doped silicon regions result in a reduced overpotentialdue to increased current flow. Furthermore, the more highly-dopedregions provide a more charged surface that attracts more strongly themetal ions from the plating solution, thus increasing the rate at whichthe reduction reaction can occur.

It is observed that if the overpotential at the silicon interface at thebase of the grooves is reduced then “ghost plating” can be minimized,and in some cases also eliminated. For example, it has been found thatif metal is deposited (e.g., by screen printing) into the base of thegrooves to make the interface more conductive, then “ghost plating” isnot observed during subsequent metal plating steps. Similarly, theamount of “ghost plating” that is observed can be reduced by increasingthe dopant density in the silicon regions at the base of the grooves.This can be achieved in the fabrication process 200 by adjusting theparameters of the laser doping process, such as the laser speed, toincrease the dopant density at the surface and to reduce the sheetresistance of interface silicon.

This approach to minimizing “ghost plating” is not limited to LIP.Electroless plating solutions are typically optimized according to arequirement to plate onto silicon having specific dopingcharacteristics. For example, often chelating agents are used toeffectively control metal ion concentrations so that plating can beachieved on both p-type and n-type silicon surfaces. Clearly, thesesolutions could be further optimized with respect to chemicalcomposition to only plate onto highly-doped n-type surfaces thusminimizing spurious plating.

Embodiments of this invention represent a significant advantage tocommercial solar cell fabrication because by solving the “ghost plating”problem in a way that does not incorporate significant further costs (interms of materials and extra processes) or result in any reductions incell performance, it enables a low-cost metallization scheme to beemployed for a new generation of solar cells that have the potential toachieve significantly higher commercial efficiencies than screen printedcells that represent the current industry standard.

Multilayer ARC and Thermal Mismatch Correction

Embodiments of solar cell manufacturing processes employing a multiplelayer dielectric which functions as an ARC and achieves thermal mismatchcorrection and ghost plating avoidance for a high efficiency commercialsolar cell are described below in which the multiple layer dielectriccan be deposited in a single process (using a single piece of equipment)or alternatively the first layer can be formed by a simple thermalprocess and the remaining layers can be formed by the single piece ofequipment.

The approach adopted is to use a double or triple layer ARC that can bedeposited in a single in-line PECVD, E-beam or sputtering depositionprocess. The first very thin layer is a thermal mismatch correctionlayer and need only be thick enough to be continuous and is expected tobe in the range of about 50 to 300 angstroms thickness. The thermalmismatch correction layer provides a thermal expansion coefficient lessthan the silicon semiconductor material being processed to ensure thesemiconductor surface is placed under compression rather than tensionwhen at elevated temperatures. This provides relief from the thermalexpansion mismatch which would otherwise be created between the ARC andthe semiconductor material, and which leads to defect generation atelevated temperatures due to the semiconductor surface being placedunder tension by the overlying ARC. Importantly, the thickness of thisfirst layer needs to be thin enough so as to not have significant impactoptically and to avoid excessive impedance of hydrogen passing throughit from the overlying hydrogen source during surface passivation of thesemiconductor material. The second layer provides the hydrogen sourcefor subsequent surface passivation of the semiconductor material. Thislayer may not have an optimum refractive index to act as an ARC but issufficiently thin to avoid detrimental effects (e.g. 80-120 angstroms ofsilicon nitride, aluminium oxide or titanium oxide). The third and byfar the thickest layer is a material such as silicon nitride, aluminiumoxide or titanium oxide deposited with the right thickness andrefractive index to provide the required antireflection opticalproperties for the ARC.

In an alternative simplified arrangement the second layer may be omittedand the third layer can be arranged to provide the hydrogen source forthe subsequent passivation step.

By way of example, when the semiconductor material from which a deviceis fabricated is crystalline silicon, this material is known to easilysustain defects when the surface is under tension, particularly if atelevated temperature. Silicon nitride, aluminium oxide or titaniumoxide, deposited by plasma enhanced chemical vapour deposition (PECVD),is known to do a good job passivating the silicon surface, bulk andgrain boundaries, primarily due to the high concentration of atomichydrogen present in the deposited silicon nitride that is able to tie updangling bonds at the silicon surface, defects or grain boundaries. Athin layer of PECVD silicon nitride in the range of 10-200 angstromsthick is therefore a good choice for the second layer when thesemiconductor is crystalline silicon.

A good choice for the first layer in this example would be silicondioxide (or silicon oxynitride) since these have a thermal expansioncoefficient less than that of silicon and can also be deposited by PECVDby appropriately varying the gases and their flow rates. The thicknessof this layer is quite important. If too thick it excessively degradesthe optical properties of the overall ARC since its refractive index isnot well suited to the requirements of the ARC. If too thin, the layeris unable to compensate for the stress created on the silicon surface bythe overlying third layer of the ARC which is significantly thicker.This second layer is generally at least as thick as the second layer (ifit exists) but not as thick as the third layer. With PECVD it ispossible to tailor this layer in terms of having a graded compositionand refractive index to further aid with the optimisation. The inclusionof some nitrogen allows silicon oxynitrides of virtually any refractiveindex from below 1.5 to above 2 to be achieved.

A good choice for the third layer is PECVD silicon nitride which can bedeposited in the same equipment and process as the first two layers. Ithas close to an ideal refractive index, while the thickness is chosen inconjunction with the thicknesses of the first two layers to overall givethe best anti-reflection properties. Typical thicknesses of the threelayers are:

-   -   i. 180 angstroms for the first layer with refractive index of        1.5-1.6;    -   ii. 100 angstroms for the second layer with refractive index of        2.0; and    -   iii. 600 angstroms for the third layer with refractive index of        2.0.

The overall reflection for this multi layer ARC is almost identical toan ideal SLARC with only about a 1% increase in reflection.

Alternatively the second and third layers can be combined into a singlesilicon nitride layer. Aluminium oxide or titanium oxide may besubstituted for one or other of the layers of silicon nitride in theexamples above.

By way of example, and with reference to FIG. 5, a suitable solar cellfabrication sequence for the formation of a silicon solar cell is asfollows:

-   -   1. Isotropic texturing 12 of the front (or light receiving)        surface of the p-type wafer 11;    -   2. front surface emitter diffusion of n-type dopant 13. The        emitter diffusion to achieve an emitter sheet resistivity of        50-250 ohms per square using either tube or belt furnace. The        emitter diffusion in finished will preferably be 80-160 ohms per        square (notionally 100 ohms per square but note that the emitter        sheet resistivity immediately following the emitter diffusion        may vary from the fatal value due to changes that occur during        processing such as slight etching back of the emitter surface        which raises the sheet resistivity)    -   3. rear surface etch/edge junction isolation/psg removal from        front surface;    -   4. ARC deposition on the front surface by PECVD;        -   a. thin 5-30 nm thermal oxide growth by belt or tube            furnace. The oxide layer is preferably grown to 10-20 nm            using an oxide growth temperature of 750-1050° C., but            preferably 900-950° C.;        -   b. PECVD deposition of silicon nitride to achieve a silicon            nitride thickness 65-75 nm. The SiNx layer may be a single            hydrogen rich layer or may comprise at least two layers (but            may be further subdivided for additional functionality) as            follows:            -   i. 80-120 angstroms (nominally 100 angstroms) of                hydrogen rich silicon nitride specifically for surface                passivation 14;            -   ii. 550-650 angstroms of silicon nitride 16 of                refractive index 2.0-2.1;    -   5. screen-print rear (non-light receiving) surface with        aluminium for the rear contact 18, followed by belt furnace        firing at 650-1,000° C. but preferably at 800-880° C. to sinter        rear contacts 18 and form back surface field 19 by formation of        aluminium/silicon alloy and liquid phase epitaxy;    -   6. formation of a dopant containing layer 17 (i.e. phosphorus        source) onto top surface;    -   7. anneal the cell to drive hydrogen from the silicon nitride        ARC into the silicon to passivate the silicon and repair damage        caused by the firing in step 5. above. A commonly used anneal        would be 400° C. for 10 mins, however the useful range is 350 to        720° C. and for 0.5 to 20 mins. This step can be performed at        any stage after step 6 and can for example be achieved by        extending the nickel sintering step below.    -   8. localised laser melting of the wafer top surface to        simultaneously melt and dope the light receiving surface of the        silicon, creating the heavily doped. (n+) regions 22 for        formation of self-aligned front surface metal contacts, while        destroying the overlying dielectric layers to expose the doped        silicon surface in preparation for self aligned metal plating        process. The laser doping of the silicon (using the externally        applied dopant source) is performed to achieve a junction depth        in the range 0.1 to 12 microns and preferably in the range 1 to        5 microns with a corresponding localised sheet-resistivity        following melting and/or evaporation of the silicon in the range        0.2 to 200 ohms per square and preferably in the range 1 to 40        ohms per square;    -   9. a dilute HF dip is performed to remove any oxide or other        surface layer on the heavily phosphorus doped silicon;    -   10. plating a layer of Nickel 23 over the laser doped n+ regions        22 for the front surface contacts. The Ni plating is performed        to provide an Ni thickness in the range of 0.01 microns to 10        microns but preferably in the range 0.1 to 1 microns    -   11. sintering of Nickel 23. The sintering step is performed at        150-500° C. and preferably in the range 350-400° C. for 0.2 to        20 minutes and preferably for 1-3 minutes. This step can be        extended to simultaneously provide the annealing step 7.    -   12. plating of layers of Copper 24 and Tin 25 (or Silver) over        the Nickel 23;    -   13. Cu plating of the laser doped lines to a thickness in the        range of 1 microns to 25 microns but preferably in the range 5        to 15 microns (nominally 8 microns)    -   14 thin silver plating to cap and protect the copper layer. The        silver plating forms a capping layer with a thickness in the        range of 0.005 microns to 1 microns but preferably in the range        0.01 to 0.1 microns (note, Cu can be eliminated and replaced by        a Ag layer of the same dimensions as the Cu layer it replaces)

The above sequence is particularly useful with multicrystalline cellsalthough it can also be used with monocrystalline cells and produces thehigh performance solar cell structure of FIG. 5 with a selective emitterthat provides heavy doping of the silicon directly beneath the metalcontacts. A controlled laser heating method may be used in conjunctionwith this manufacturing sequence to reduce the formation of defects inthe region of the contacts.

Improved heating regimes can be effected by a uniquely designed laserQ-switching arrangement or by a scanning continuous wave laser withappropriate power level, to melt the silicon for adequate duration tofacilitate dopant mixing while simultaneously avoiding unnecessarythermal cycling of the melted regions or ablation of the doped silicon.Q-switched laser systems or directly applied continuous wave lasersoperated in the conventional manner are unable to heat and melt thesilicon in the required way.

By keeping the oxide layer thin enough so as not to act as too severe abarrier to the passage of atomic hydrogen from the overlying hydrogensource layer into the silicon to passivate the grain boundaries, theissues relating to the use of an oxide layer can be largely overcome.

Such a thin thermally grown oxide would normally never be used inconjunction with multi wafers because it blocks/retards the atomic Hfrom getting through to passivate the crystallographic defects and grainboundaries, however using the sequence described above this difficultycan be overcome.

The use of the thin oxide is also important in multicrystalline siliconfor stopping ghost plating in the emitter metallization steps as suchwafers usually have different type of texturing with holes in the thatare hard to coat properly with silicon nitride and are therefore moreprone to ghost plating.

The use of a thermal oxide (normally grown in the range of 900-980° C.)would normally be considered to be a performance degrading feature as itdamages the silicon quality for multicrystalline wafers (which is notthe case for monocrystalline wafers). This effect is well documented. Inthe present sequence, the anneal to improve the hydrogen passivationseems to rectify damage caused by the high temperatures used in theoxide growth step.

Laser Doping Process

The laser doping process for a silicon wafer involves melting localisedsurface regions of the wafer in the presence of either n-type or p-typedopants, so that the dopants are incorporated into the molten region.Referring to FIG. 5, this facilitates the formation of a selectiveemitter structure with the heavily doped regions 22 self-aligned to theoverlying metal contact 23, 24, 25. The dopants can be included within asurface dielectric layer 17, be applied as a coating on top of or belowthe dielectric layer (also potentially the antireflection coating 16),they may be present in the silicon in an unactivated state whereby theyare absorbed into the silicon structure (or activated) by the meltingand refreezing process or they may be applied to the region in gaseousor liquid form whilst the silicon is molten (described below withreference to FIGS. 6 and 7). Referring to the FIG. 1 example, to uselaser doping in conjunction with subsequently forming self aligned metalcontacts 23, 24, 25 onto the highly doped laser melted regions 22, thesilicon surface is coated with a dielectric layer 17 that protects theunmelted regions from the subsequent metal contact formation process astaught by Wenham and Green, U.S. Pat. No. 6,429,037. The laser dopingprocess automatically destroys the overlying dielectric layer in thelaser doped regions, therefore exposing the silicon surface forsubsequent metal contact formation which can be done in a self-alignedprocess such as via metal plating. The dielectric layer or layers caninclude an antireflection coating 16, surface passivation layer 14,dopant source 17, hydrogen source (not shown) for surface and/or grainboundary and/or defect passivation, protection layer (also not shown)for the silicon surface and/or plating mask, or one or more layers whichpotentially in combination or singly perform one or more of thesefunctions.

The dopant source may also be incorporated within the silicon itself,rather than in a separate layer or coating. In other words, the lasermay be used to locally melt the silicon that is already loaded withdopant such that the melting and refreezing process causes the freedopants (commonly referred to as interstitial atoms which areelectrically inactive dopants that are not bonded normally within thesilicon lattice) to be absorbed into the crystalline silicon structure(lattice) and redistributed from original location. For example when ann-type dopant is thermally diffused into the surface of the silicon inan emitter forming step, many more n-type dopant atoms may be diffusedinto the silicon than actually become electrically active. Laser meltingcan then be used to allow these extra dopant atoms to redistributethemselves and become active within the silicon to form more heavilydoped contact regions.

The number of inactive dopants that will be present within the silicon(e.g. within the diffused n-type emitter) is determined by the way inwhich the diffusion is done. Often when diffusing dopant into a surfaceit will be done it in a way that attempts to keep the surfaceconcentration of the dopant (e.g. phosphorus (P)) below the solidsolubility of the dopant in Silicon, for the particular temperature atwhich the processing is being performed, to avoid the inclusion of toomany inactive dopants. One way of avoiding excessive dopant atoms in thesilicon, for example, is by diffusing through a silicon dioxide layer(most common approach) although another very common approach is simplyto reduce the concentration of the dopant source.

By deliberately allowing the surface dopant concentration (e.g.phosphorous) to go above the solid solubility of the dopant in silicon,whereby large numbers of inactive dopants are incorporated into thesurface, these inactive dopants can become the source of dopants for thelaser doping process. Typically the emitter will be formed with a sheetresistivity in the range of 80-200 ohms per square. By incorporating alarge number of inactive dopants, the sheet resistivity can be reducedby at least a factor of two in the areas treated by the laser comparedto the areas not treated by the laser. For example, if the emitter isformed with a preferred emitter sheet resistivity of 100 ohms persquare, this can be made to drop to about 30-40 ohms per square in areasmelted by the laser. This level of sheet resistivity is sufficient forgood performance but optimisation of the process may provide even betterresults.

FIG. 12 schematically illustrates the arrangement of a laser and liquidjet when used to process a substrate provided with a dielectric surfacelayer. In this case the surface layer need not provide a dopant source.As illustrated, a laser 60 emitting a laser beam 61 is projected througha covered window 62 in a nozzle unit 63. A liquid jet 64 is generated bythe nozzle unit into which the laser beam 61 is coupled such that it maybe guided by total internal reflection towards the target. A supply ofliquid to the nozzle unit 63 is provided through ports 65 and isexpelled through a nozzle orifice 66 which projects the liquid towardsthe target. The window 62 is oriented to receive a vertical laser beam61 which is directed axially into the liquid jet 64. The laser beam 61is focussed by appropriate lenses 67 before entry through the window 62.Liquid is delivered to the nozzle unit 63 with a pressure of between 20to 500 bar via the liquid supply port 65. The liquid may be suppliedfrom a reservoir 72 or other suitable source and pumped under pressureto the nozzle unit 63 by supply pump 73. The liquid may also be heatedby heater 74 so that the temperature of the liquid jet may becontrolled. The generated liquid jet 64 may have a diameter in the rangeof approximately 20 to 100 μm.

The liquid jet 66 and laser beam 61 are shown directed to a target whichis a 250 μm silicon substrate 68 with a 30-80 nm thick silicon nitridelayer surface layer 69 overlying a thin oxide layer 70. The liquid jet64 and laser beam 61 are guided over regions of the surface layer aswith conventional laser doping methods. By adding phosphoric acid to theliquid jet a strong corrosive action will take place on the siliconnitride layer and the underlying silicon where the surface becomesheated by the laser beam 61 leaving the surface layer 69 very cleanlyand precise ablated, whereas the substrate 68 is left substantiallyintact elsewhere. Additives are added to the liquid jet 64 from one ormore supply tanks 75 and injected by respective pumps 76 into the portal77 of the nozzle unit 63. However n-type doping of a surface region 71of the silicon can also be performed simultaneously with the nitrideremoval by virtue of the phosphoric acid used for cleaning, or by theinclusion of additional dopant additives such as POCl3, PCl3, PCl5, or amixture of these. P-type doping could also be achieved in a similaroperation by selecting the appropriate dopants (e.g. Boron).

The liquid jet 66 and laser beam 61 may also be used with dopant sourcesincluded within a surface dielectric layer 17, sources applied as acoating on top of or below the dielectric layer (also potentially theantireflection coating 16), or the dopant atoms may be present in thesilicon in an unactivated state whereby they are absorbed into thesilicon structure (or activated) by the melting and refreezing processas described above with reference to other laser systems.

Laser operations may also be performed in a gaseous environment toachieve the doped surface region 71 without providing dopant in theliquid jet. Referring to FIG. 13, in this case the laser 60 emits laserbeam 61 which is directed through a window 82 in a chamber 81 containingthe target substrate 68. A dopant source in gaseous form is suppliedfrom a pressurised storage cylinder 85 via control valve 84 and port 83,into the chamber 81. Gas is expelled from the chamber via exhaust port86 and exhaust vale 87 to a disposal passage 88. The laser is scannedover the surface of the substrate 68 as before, melting theantireflection coating 69 and a portion of the underlying surfacewhereby the gaseous dopant is absorbed into the molten silicon surfacematerial to form the doped surface layer 71.

While the use of a gaseous environment is described above in conjunctionwith the use of a laser beam projected within a liquid jet the gaseousenvironment may equally be employed with any of the other laserarrangements described above that are not associated with a liquid jet.Liquid dopant sources may also be employed with any of the laserarrangements described, other than as a liquid jet through which thelaser beam is projected. The liquid source may be pooled or flowed overthe surface which is being doped or may be applied as a jet directed atthe point of laser heating.

It will be appreciated by persons skilled in the art that numerousvariations and/or modifications may be made to the invention as shown inthe specific embodiments without departing from the scope of theinvention as broadly described. The present embodiments are, therefore,to be considered in all respects as illustrative and not restrictive.

The invention claimed is:
 1. A method of forming emitter contacts on asurface emitter of a silicon solar cell comprising a substrate ofsilicon material, the method comprising: (i) forming the surface emitterby performing an n-type diffusion of a surface of the substrate to forman emitter surface layer; (ii) etching back the surface of the substrateto achieve a dopant concentration at the surface of the substrate ofless than 10²⁰ atoms/cm³; (iii) depositing a surface dielectric layer orlayers onto the etched back surface of the substrate; (iv) patterningthe dielectric layer or layers in localized areas to expose regions of asilicon surface of the substrate where contacts are to be formed; and(v) selectively plating the silicon surface of the substrate in theexposed regions where contacts are to be formed to make an electricalconnection to the emitter surface layer.
 2. The method of claim 1wherein the emitter surface layer is formed with a sheet resistance inthe range of 10-40 Ω/square.
 3. The method of claim 1 wherein depositingthe surface dielectric layer or layers onto the etched back surface ofthe substrate comprises: a. growing a thin 5-30 nm silicon oxide layer;and b. PECVD deposition of an Anti-Reflection Coating (ARC).
 4. Themethod of claim 3 wherein the thin silicon oxide layer is grown to athickness of 10-20 nm.
 5. The method as claimed in claim 3 wherein theARC layer has a thickness of 65-75 nm and a refractive index of 2.0-2.1.6. The method as claimed in claim 3 wherein the ARC layer is a singlehydrogen rich layer.
 7. The method as claimed in claim 3 wherein the ARClayer comprises at least two layers as follows: i. 80-120 angstroms ofhydrogen rich material; and ii. 550-650 angstroms of material ofrefractive index 2.0-2.1.
 8. The method as claimed in claim 3 whereinthe ARC comprises a layer or layers of silicon nitride, aluminium oxide,titanium oxide, or a combination of these.
 9. The method as claimed inclaim 8 wherein the ARC comprises a layer or layers of silicon nitride.10. The method of claim 1 wherein the surface dielectric layer or layerscomprises a layer of hydrogen rich material.
 11. The method of claim 10further comprising annealing the substrate to drive hydrogen from thelayer of hydrogen rich material into the substrate to passivate thesilicon material.
 12. The method as claimed in claim 1 wherein annealingis performed at a temperature in the range of 350 to 720° C. for 0.5 to20 mins.
 13. The method as claimed in claim 12 wherein annealing isperformed at a temperature in the range of 350 to 500° C. for 5 to 20mins.
 14. The method as claimed in claim 12 wherein annealing isperformed at a temperature in the range of 380 to 420° C. for 8to 12mins.
 15. The method of claim 12 wherein annealing is performed at atemperature in the range of 500 to 720° C. for 0.5 to 8 mins.
 16. Themethod of claim 10 wherein the hydrogen rich material is siliconnitride.
 17. The method of claim 1 wherein patterning the dielectriclayer or layers comprises performing a localised laser melting of thesilicon substrate surface through the surface dielectric in the presenceof a dopant containing source to simultaneously melt and dope thesurface of the substrate, creating doped silicon n+ regions, which aremore heavily doped than the emitter surface layer, in the regions wherethe front surface metal contacts are to be formed, while destroying theoverlying dielectric layer or layers to expose a surface of the moreheavily doped silicon n+ regions.
 18. The method of claim 17 whereinselectively plating comprises plating a layer of nickel over the moreheavily doped silicon n+ regions.
 19. A method of forming emittercontacts on a surface emitter of a silicon solar cell comprising asubstrate of silicon material, the method comprising: (i) forming thesurface emitter by performing an n-type diffusion of a surface of thesubstrate to form an emitter surface layer with a pn junction depth ofat least 1.5 μm; (ii) etching back the surface of the substrate toachieve a dopant concentration at the surface of the substrate to lessthan 10²⁰ atoms/cm³ and to increase a sheet resistance of the emittersurface layer to 100-160 Ω/square; (iii) depositing a surface dielectriclayer or layers onto the etched back surface of the substrate; (iv)patterning the dielectric layer in localized areas to expose regions ofa silicon surface of the substrate where contacts are to be formed; (v)doping the surface of the substrate in the exposed regions wherecontacts are to be formed whereby a dopant concentration at the surfaceof the exposed regions is greater than the dopant concentration at thesurface of the substrate over a remainder of the surface of thesubstrate by a factor of at least two; and (vi) selectively plating thesilicon surface of the substrate in the exposed regions where contactsare to be formed to make an electrical connection the emitter surfacelayer.